The MIPI (Mobile Industry Processor Interface) alliance is known as an organization which develops specifications of communication interfaces. The MIPI specifications, which are standardized by the MIPI alliance, are widely used for communications between hosts (e.g. processors) and peripheral devices (e.g. display devices).
MIPI D-PHY is one of the MIPI specifications, which is most typically used for communications between an application processor and a display module in a portable device. In MIPI D-PHY interfacing, communications are achieved with one clock lane and one to four data lanes. Each lane includes a pair of signal lines transmitting a low-amplitude differential signal. The clock lane is used to transmit a differential clock signal, and each data lane is used to transmit a differential data signal. When the communication interface is placed in the HS (high speed) mode, in which high-speed communications are implemented, the transmitting side transmits a differential clock signal over the clock lane and a set of differential data signals over the data lanes. The receiving side achieves data reception by latching the differential data signals transmitted over the data lanes in synchronization with the differential clock signal transmitted over the clock lane. Note that Japanese Patent Application Publication No. 2014-168195 A discloses a communications system operated in accordance with the MIPI D-PHY specification.
Recent enhancement in the display resolution of display panels has necessitated high-speed transmission of image data, and therefore communication interfaces are required to operate at a higher speed. The MIPI C-PHY specification is a newly-defined specification developed to meet this requirement. In a MIPI C-PHY system, communications are achieved with three signal lines. The signal lines respectively transmit three-valued low-amplitude signals (which are allowed to take three values: “high”, “low” and “middle”) and the three-valued signals are converted into a binary logic signal on the reception side. One feature of MIPI C-PHY is that the clock is embedded in data signals; the reception side performs clock recovery in receiving the data signals.
Although the use of MIPI C-PHY effectively achieves high-speed communications, it is not necessarily easy to use a newly-defined communication specification. Accordingly, some users may desire to adopt the MIPI D-PHY specification and other users may desire to adopt the MIPI C-PHY specification. It would be desirable if vendors provide semiconductor devices adapted to both of these two specifications.
In a simplest approach, both of a communication interface supporting the MIPI D-PHY specification and a communication interface supporting the MIPI C-PHY specification may be monolithically integrated in a semiconductor integrated circuit; however, simply integrating multiple independent communication interfaces into one semiconductor device undesirably increases the circuit size.
Accordingly, there is a technical need for providing a semiconductor device supporting both of the MIPI D-PHY and MIPI C-PHY specifications with a reduced circuit size.